Deep Learning with FPGA

This chapter presents recent papers for using FPGAs (Field Programmable Gate Arrays) for Deep Learning. FPGAs can roughly be seen as a Software-configurable Hardware, i.e you in some cases get close to dedicated hardware speed (although typically at lower clock frequency than chips, but typically with strong on-FPGA parallelism), this can be a potential good fit for e.g. Convolutional Neural Networks since they require many convolutional layer calculations (with many convolutional filters per conv.layer) with large tensors. Recommend starting with having a look at Deep Learning on FPGAs: Past, Present, and Future

Best regards,

Amund Tveit

Convolutional Neural Network

  1. Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
    – Authors: N Suda, V Chandra, G Dasika, A Mohanty, Y M (2016)
  2. Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA
    – Authors: P Meloni, G Deriu, F Conti, I Loi, L Raffo, L Benini (2016)
  3. Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs
    – Authors: R Tapiador, A Rios (2016)
  4. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
    – Authors: C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong (2015)
  5. Musical notes classification with Neuromorphic Auditory System using FPGA and a Convolutional Spiking Network
    – Authors: E Cerezuela (2015)
  6. CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis
    – Authors: M Zhu, L Liu, C Wang, Y Xie (2016)
  7. Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
    – Authors: C Zhang, D Wu, J Sun, G Sun, G Luo, J Cong (2016)

 

Other uses of FPGA in Deep Learning

  1. Deep Neural Network Architecture Implementation on FPGAs Using a Layer Multiplexing Scheme
    – Authors: F Ortega (2016)
  2. FPGA Based Multi-core Architectures for Deep Learning Networks
    – Authors: H Chen (2016)
  3. FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines
    – Authors: K Ueyoshi, T Marukame, T Asai, M Motomura… (2016)
  4. DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
    – Authors: C Wang, Q Yu, L Gong, X Li, Y Xie, X Zhou (2016)
  5. Deep Learning on FPGAs
    – Authors: Gj Lacey (2016)
  6. DNNWEAVER: From High-Level Deep Network Models to FPGA Acceleration
    – Authors: H Sharma, J Park, E Amaro, B Thwaites, P Kotha (2016)
  7. Handwritten Digit Classification on FPGA
    – Authors: K Kudrolli, S Shah, Dj Park (2016)
  8. Fpga Based Implementation of Deep Neural Networks Using On-chip Memory Only
    – Authors: J Park, W Sung (2016)
  9. FPGA Implementation of Autoencoders Having Shared Synapse Architecture
    – Authors: A Suzuki, T Morie, H Tamukoh (2016)
  10. Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale
    – Authors: M Huang, D Wu, Ch Yu, Z Fang, M Interlandi, T Condie… (2016)
  11. A Deep Learning Prediction Process Accelerator Based FPGA
    – Authors: Q Yu, C Wang, X Ma, X Li, X Zhou (2015)
  12. FPGA implementation of a Deep Belief Network architecture for character recognition using stochastic computation
    – Authors: K Sanni, G Garreau, Jl Molin, Ag Andreou (2015)
  13. An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version)
    – Authors: T Horita, I Takanami, M Akiba, M Terauchi, T Kanno (2015)
  14. Efficient Generation of Energy and Performance Pareto Front for FPGA Designs
    – Authors: Sr Kuppannagari, Vk Prasanna (2015)
  15. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
    – Authors: C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong (2015)
  16. Musical notes classification with Neuromorphic Auditory System using FPGA and a Convolutional Spiking Network
    – Authors: E Cerezuela (2015)
  17. FPGA Acceleration of Recurrent Neural Network based Language Model
    – Authors: S Li, C Wu, Hh Li, B Li, Y Wang, Q Qiu (2015)
  18. FPGA emulation of a spike-based, stochastic system for real-time image dewarping
    – Authors: Jl Molin, T Figliolia, K Sanni, I Doxas, A Andreou… (2015)
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